1. Field of the Invention
The present invention relates to a structure of a static semiconductor memory device, and more particularly, it relates to a structure of a static semiconductor memory device which can implement a high-speed operation with low power consumption while suppressing increase of a memory cell area at a low power supply voltage.
2. Description of the Background Art
A conventional static semiconductor memory device is now described with reference to a static random access memory (hereinafter referred to as SRAM).
FIG. 43 is a schematic block diagram showing the structure of a read-system circuit of a conventional SRAM 3000.
The read-system circuit of the conventional SRAM 3000 comprises a precharge circuit 3002 for precharging a pair of bit lines BL and /BL at an internal power supply potential before starting a read operation, a memory cell 3004 connected with the pair of bit lines BL and /BL, constant current sources 3006a and 3006b for supplying prescribed constant currents to the bit lines BL and /BL respectively, and a read circuit 3008 for receiving the potentials of the pair of bit lines BL and /BL and outputting read data.
The memory cell 3004 includes a static latch circuit which is formed by invertors 3010 and 3012 whose inputs and outputs are connected with each other, and access transistors 3014 and 3016 for switching connection between the pair of bit lines BL and /BL and input/output nodes of the static latch circuit in response to the potential level of a word line WL.
FIG. 44 is a circuit diagram showing the structure of the memory cell 3004 shown in FIG. 43 in detail.
Referring to FIG. 44, the memory cell of the conventional SRAM includes driver transistors Q1 and Q2, access transistors Q3 and Q4, and high-resistance elements R1 and R2. The driver transistors Q1 and Q2 and the access transistors Q3 and Q4 are N-channel MOS transistors. The high-resistance elements R1 and R2 are employed as load elements of the memory cell.
The gate of the driver transistor Q1 is connected with the drain (storage node N2) of the driver transistor Q2, while the gate of the driver transistor Q2 is connected with the drain (storage node N1) of the driver transistor Q1.
Namely, an invertor formed by the high-resistance element R1 and the driver transistor Q1 is cross-connected with an invertor formed by the high-resistance element R2 and the driver transistor Q2, thereby forming a latch circuit. The access transistor Q3 is connected between the bit line BL and the storage node N1, and its gate is connected to the word line W.
The access transistor Q4 is connected between the bit line/BL and the storage node N2, and its gate is connected to the word line WL. The high-resistance element R1 is connected between a node which is supplied with a power supply potential Vcc and the storage node N1. The high-resistance element R2 is connected between another node which is supplied with the power supply potential Vcc and the storage node N2.
Such a memory cell is generally called a high-resistance load memory cell.
Such a high-resistance load memory cell generally has the following stereoscopic structure, in order to reduce the area of the memory cell:
The driver transistors Q1 and Q2 and the access transistors Q3 and Q4 are formed on a major surface of a silicon substrate (not shown). Load elements (the high-resistance elements R1 and R2) of the high-resistance load memory cell, which are made of polysilicon, are formed above the major surface through an insulating layer.
FIG. 45 is a circuit diagram showing a memory cell of another conventional SRAM. Portions similar to those in FIG. 44 are denoted by the same reference numerals, to omit redundant description.
Referring to FIG. 45, the memory cell of the conventional SRAM includes driver transistors Q1 and Q2, access transistors Q3 and Q4, and P-channel MOS transistors Q5 and Q6.
The P-channel MOS transistor Q5 is connected between a node which is supplied with a power supply potential Vcc and a storage node N1, and its gate is connected to another storage node N2.
The P-channel MOS transistor Q6 is connected between another node which is supplied with the power supply potential Vcc and the storage node N2, and its gate is connected to the storage node N1. The P-channel MOS transistors Q5 and Q6 are employed as load elements of the memory cell. Such a memory cell is generally called a CMOS memory cell.
The P-channel MOS transistors Q5 and Q6 serving as load elements are formed by thin-film transistors. These thin-film transistors are formed above a major surface of a silicon substrate (not shown) which is provided with the transistors Q1 to Q4, through an insulating layer (not shown).
FIG. 46 shows transfer characteristics of the memory cell of the conventional SRAM shown in FIG. 44 or 45 obtained when the word line WL is in a selected state. It is assumed here that the SRAM is supplied with a power supply potential Vcc of 3 V, for example.
Referring to FIG. 46, the axes of ordinates and abscissas show the potentials of the storage nodes N1 and N2 shown in FIG. 44 or 45 respectively. With reference to FIGS. 44 or 45 and 46, a first problem of the conventional SRAM is now described.
Referring to FIG. 46, arrow A shows two stable points of the memory cell. Presence of the two stable points is necessary for reliably holding data stored in the memory cell, i.e., for preventing the data stored in the memory cell from destruction.
The two stable points can be ensured by sufficiently increasing the size of regions (hereinafter referred to as "eyes of the memory cell") shown by arrow B. The eyes of the memory cell may also be referred to as static noise margins.
The inclination of a curve shown by arrow C shows the gain levels of the invertors of the memory cell. The invertors of the memory cell have high gains when the curve shown by arrow C is steeply inclined, while the invertors have low gains when the curve C is loosely inclined.
When the load elements of the memory cell are formed by the high-resistance elements R1 and R2 or the thin-film transistors Q5 and Q6, ON-state resistances of these load elements are considerably larger than those of the driver transistors Q1 and Q2 and the access transistors Q3 and Q4. When the word line WL is selected, i.e., supplied with the power supply potential Vcc, therefore, the invertor gains of the memory cell are lowered and the eyes thereof are reduced in size.
In other words, the characteristics of the memory cell are not decided by the invertor formed by the high-resistance element R and the transistor Q1 and that formed by the high-resistance element R2 and the transistor Q2 in FIG. 44 or 45, for example, but the static noise margins are rather decided by the characteristics of a circuit formed by serially connecting the access transistor Q3 with the driver transistor Q1 and that formed by serially connecting the access transistor Q4 with the driver transistor Q2. Namely, this is equivalent to such a state that the load elements are formed by the N-channel MOS transistors Q3 and Q4, and hence the gains of the invertors are lowered and the eyes of the memory cell are disadvantageously reduced in size.
In order to reliably hold the data of the memory cell, therefore, the following design is necessary: Assuming that Wd and Ld represent the channel width and the channel length of the driver transistors Q1 and Q2 respectively, and Wa and La represent those of the access transistors Q3 and Q4 respectively, the ratio Wd/Ld must generally be at least about three times the ratio Wa/La, in order to increase the gains thereby increasing the eyes of the memory cell in size. Thus, the areas of the driver transistors Q1 and Q2 are disadvantageously increased, to inhibit reduction of the area of the memory cell. This is the first problem of the conventional SRAM.
FIG. 47 shows transfer characteristics of the memory cell obtained when the conventional SRAM is driven at a power supply potential Vcc of 2 V and the word line WL is in a selected state.
Referring to FIG. 47, the axes of ordinates and abscissas show the potentials of the storage nodes N1 and N2 shown in FIG. 44 or 45 respectively. A second problem of the conventional SRAM is now described.
Referring to FIG. 47, eyes of the memory cell are disadvantageously reduced in size in the conventional SRAM having the memory cell shown in FIG. 44 or 45 when a low power supply potential Vcc of 2 V is employed. Thus, two stable points may disappear in a high possibility, and the memory cell cannot hold the data in this case. This is the second problem of the conventional SRAM.